In two stage page table translation process, I think stage-1 is in el1 and the guestOS is responsible for translating by TTBR0_EL1. As for stage-2 translation, I think the hypervisor in EL2 is responsible for this. In stage-2 translation, VTTBR_EL2 is used. After stage-1 translation, how does the exception level change so that the system can access register in EL2？Could someone describe the detail of two stage translation, including related registers, assembly instruction and how the exception level changes.
In aarch64 two stage page table translation, how will the exception level change?
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