Is it Possible for a Thread to Read Stale Data Due to CPU Core Switching in a Multi-threaded Environment?

Question

Consider this scenario: In a multi-threaded application, there is a shared variable that is modified by only one thread (let's call it Thread A) but read by several other threads (Thread B, C, D).

Here's the sequence of events:

1. Thread A updates the value of the shared variable to 1.
2. Threads B, C, and D read the value as 1.
3. Thread A then changes the value to 2.
4. Now, imagine that the OS scheduler moves Thread A to the CPU core previously used by Thread B. Thread A proceeds to read the shared variable again. Given that the last read on this CPU core yielded a value of 1, the L1 cache on this core might still contain the stale value of 1.

This leads to an unusual situation: from Thread A's perspective, the value has unexpectedly reverted to its previous state.

Is such a scenario plausible, especially on CPUs based on the ARM architecture?

Answer 1

If that scenario were realistic...

Nope! Jeremy Friesner is right. I was wrong. What is "realistic" does not matter. What matters is

1. More than one thread accesses the same variable,
2. At least one access is a write,
3. At least one access is unsynchronized.

If all three of those conditions are met, then the behavior of the program is undefined. What is or is not "realistic" is beside the point. Maybe knowing what is or is not "realistic" might be of some use if you've been assigned to analyze a crash dump and satisfy some micro-manager who demands to know precisely what went wrong, but if you're trying to predict how the program will behave in the future, it's undefined. End of story.