cache coherence - Why are some steps considered exclusive?

Question

Given this prelude:

consider a system with 2 cores, P1 and P2 using write back and write allocate schemes.

the addresses A1 and A2 are mapped to the same cache block but A1 IS not equal A2. Initial cache is invalid. Use the MESI protocol here.

The following steps are taken:

1. P1 writes the value 10 to A1
2. P1 reads the value at A1
3. P2 reads the value at A1
4. P2 writes the value of 20 to A1
5. P2 writes the value of 40 to A2
6. P1 reads the value at A1

I'm wondering, in step 1 why is that action of P1 writing to A1 considered as 'exclusive'? I would've thought that it would be 'modified' considering that we are writing to the address?

This example is taken from this source http://people.eecs.berkeley.edu/~pattrsn/252F96/Lecture18.pdf

Here is the end state table:

Could someone explain why Steps 1 and 4 are considered "exclusive" and not modified?