Is there any way to flush the cache line to the L3 cache?

Question

I am a PhD student in the direction of architecture. I am doing some research work on cache.

Is there any way to flush the cache line to the L3 cache? For example, there are some cache lines in the L1 and L2 caches, and I want to adjust them to the L3 cache. Because my experiment is to ensure that access to these cache lines has a similar time delay. The clflush instruction flushes all cache lines to memory. I just want to flush to L3 cache.

My server is configured as:

$ lscpu
Architecture:          x86_64
CPU mode：    32-bit, 64-bit
Byte Order:            Little Endian
CPU(s):                48
On-line CPU(s) list:   0-47
Thread(s) per core：2
Core(s) per socket：  12
Socket(s):             2
NUMA node(s):         2
Vendor ID:           GenuineIntel
CPU family:          6
Model:               79
Model name:            Intel(R) Xeon(R) CPU E5-2650 v4 @ 2.20GHz
Stepping:               1
CPU MHz：             1200.614
CPU max MHz:           2900.0000
CPU min MHz:           1200.0000
BogoMIPS:              4401.87
L1d cache：          32K
L1i cache：          32K
L2 cache：           256K
L3 cache：           30720K
NUMA node0 CPU(s):     0,2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38,40,42,44,46
NUMA node1 CPU(s):     1,3,5,7,9,11,13,15,17,19,21,23,25,27,29,31,33,35,37,39,41,43,45,47
Flags:                 fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm p                  be syscall nx pdpe1gb rdtscp lm constant_tsc arch_perfmon pebs bts rep_good nopl xtopology nonstop_tsc cpuid aperfmperf pni pclmulqdq dtes64                   monitor ds_cpl vmx smx est tm2 ssse3 sdbg fma cx16 xtpr pdcm pcid dca sse4_1 sse4_2 x2apic movbe popcnt tsc_deadline_timer aes xsave avx f1                  6c rdrand lahf_lm abm 3dnowprefetch cpuid_fault epb cat_l3 cdp_l3 invpcid_single pti ssbd ibrs ibpb stibp tpr_shadow vnmi flexpriority ept v                  pid fsgsbase tsc_adjust bmi1 hle avx2 smep bmi2 erms invpcid rtm cqm rdt_a rdseed adx smap intel_pt xsaveopt cqm_llc cqm_occup_llc cqm_mbm_t                  otal cqm_mbm_local dtherm ida arat pln pts md_clear flush_l1d

Answer 1

Currently, no. But Intel promises to add a new instruction called cldemote to achieve what you describe in its future Alder Lake server processor, which is, however, not commercially available yet.

• Instruction Specification: https://www.felixcloutier.com/x86/cldemote
• Report on this: https://www.dsogaming.com/news/intels-future-alder-lake-s-cpu-architecture-to-feature-cldemote-cache-line-demote-instruction-set/
• A good article written by Dr.Bandwidth to introduce cldemote: https://sites.utexas.edu/jdm4372/2019/02/18/intels-future-cldemote-instruction/