I am implementing implementing a simple cache hierarchy with 64KB L1 Dcache, 64KB L1 Icache and a unified 4MB L2 cache (all exclusive).
I ran CPU2006 sjeng benchmark and I got the following stats:
- system.cpu.dcache.overallMisses::total 2368294 # number of overall misses (Count)
- system.cpu.icache.overallMisses::total 564 # number of overall misses (Count)
- system.l2.overallHits::total 36 # number of overall hits (Count)
- system.l2.overallMisses::total 3279 # number of overall misses (Count)
I was assuming that the total L1 miss should be equal to L2 Hit+Miss, but there is a huge difference in the numbers. Can someone please help me on how to relate them.