MIPS pipeline forwarding

Question

Consider a 5-stage pipelined processor with Instruction Fetch (IF), Instruction Decode (ID), Execute (EX), Memory Access (MEM), and Register Writeback (WB) stages. Which of the following statements about forwarding is/are CORRECT?

A) In a pipelined execution, forwarding means the result from a source stage of an earlier instruction is passed on to the destination stage of a later instruction
B) In forwarding, data from the output of the MEM stage can be passed on to the input of the EX stage of the next instruction
C) Forwarding cannot prevent all pipeline stalls
D) Forwarding does not require any extra hardware to retrieve the data from the pipeline stages

Would option B be one of the correct answers? If yes, then kindly provide proper references from authors/research papers for the same.

Option a will be true for non-linear pipelines while option C is definitely true and we can find many examples of pipelined systems for the same. Option D is clearly false. My only confusion is regarding option B.

Answer 1

A first instruction does

cycle	stage
1	IF
2	ID
3	EX
4	MEM
5	WB

And thus a second instruction has the following timing:

cycle	stage
2	IF
3	ID
4	EX
5	MEM
6	WB

Let's say there is a RAW dependency between the first and second instruction on MEM stage (then the first instruction is a load whose result available after its MEM, and the second instruction computes with that load result, using it in its EX).

In that scenario, the first instruction's MEM stage is at cycle 4 and so is the second instruction's EX stage.  The second instruction's EX stage will have to be delayed in order for this forward to work.

We can indeed forward from MEM to EX but only in the next cycle after MEM, so for a load-use RAW hazard, both a forward and a delay/stall cycle are required, meaning the load's MEM stage in cycle 4 and the next instruction's EX in cycle 5.

This makes the question tricky, since you could answer both ways:

• no, we cannot forward from MEM to EX of a next instruction, since those both occur in the same cycle.
• yes, we can forward from MEM to EX of a next instruction, but a delay/stall cycle is also required.

With the stall and forward the second instructions timing becomes:

cycle	stage
2	IF
3	ID
4	EX*
5	EX
6	MEM
7	WB

*this cycle is wasted, and must be repeated