I need help with a basic PT setup with hierarchal netlist.
Context:
- I have a design named top.v as described in diagram below:-
- TOP has two modules (CELL_A and CELL_B)
- CELL_A has one flop=FLOP1
- CELL-B has one flop=FLOP2
Commands I am running :
- read_verilog top.v
- set link_path “flop1.corner.db flop2.corner.db”
- link_design top
With above I am getting any useful error, but my design in not linked properly. Please refer the log snippet below:
Please advice if I am doing anything fundamentally wrong here.