Register values not showing at the correct time in testbench simulation

Question

Based on research, the input value to a flip flop is read during one rising/falling edge and output at the next rising/falling edge, however, I'm not seeing this behavior in my test bench.What I believe I'm seeing is that the output values are being seen during the same rising edge when they are being read, which is incorrect. A screen shot of simulation is shown below where the input, Atten, which has the value 3f, is being seen at the output, DBA_TX1_DSA, at the same rising edge where it seems to be read.

The vhdl code used along withe test bench are also shown below.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;


--Inputs and outputs to entity 
entity DSA_Worker is
    Port ( DB_Select : in STD_LOGIC;
           Atten : in STD_LOGIC_VECTOR ( 7 downto 0);
           enable : in STD_LOGIC;
           clk: in STD_LOGIC;
           reset: in STD_LOGIC;
           chip_select : in STD_LOGIC_VECTOR (1 downto 0);
           DBA_TX1_DSA : out STD_LOGIC_VECTOR (7 downto 0);
           DBA_TX2_DSA : out STD_LOGIC_VECTOR (7 downto 0);
           DBA_RX1_DSA : out STD_LOGIC_VECTOR (7 downto 0);
           DBA_RX2_DSA : out STD_LOGIC_VECTOR (7 downto 0);
           DBB_TX1_DSA : out STD_LOGIC_VECTOR (7 downto 0);
           DBB_TX2_DSA : out STD_LOGIC_VECTOR (7 downto 0);
           DBB_RX1_DSA : out STD_LOGIC_VECTOR (7 downto 0);
           DBB_RX2_DSA : out STD_LOGIC_VECTOR (7 downto 0));
end DSA_Worker;

architecture Behavioral of DSA_Worker is

begin
process(clk)
begin
  if rising_edge(clk) then
  --if reset is high, all outputs go to 0
     if reset = '1'then
       DBA_TX1_DSA(0) <= '0';
       DBA_TX1_DSA(1) <= '0';
       DBA_TX1_DSA(2) <= '0';
       DBA_TX1_DSA(3) <= '0';
       DBA_TX1_DSA(4) <= '0';
       DBA_TX1_DSA(5) <= '0';
       DBA_TX2_DSA(0) <= '0';
       DBA_TX2_DSA(1) <= '0';
       DBA_TX2_DSA(2) <= '0';
       DBA_TX2_DSA(3) <= '0';
       DBA_TX2_DSA(4) <= '0';
       DBA_TX2_DSA(5) <= '0';
       DBA_RX1_DSA(0) <= '0';
       DBA_RX1_DSA(1) <= '0';
       DBA_RX1_DSA(2) <= '0';
       DBA_RX1_DSA(3) <= '0';
       DBA_RX1_DSA(4) <= '0';
       DBA_RX1_DSA(5) <= '0';
       DBA_RX2_DSA(0) <= '0';
       DBA_RX2_DSA(1) <= '0';
       DBA_RX2_DSA(2) <= '0';
       DBA_RX2_DSA(3) <= '0';
       DBA_RX2_DSA(4) <= '0';
       DBA_RX2_DSA(5) <= '0';
       DBB_TX1_DSA(0) <= '0';
       DBB_TX1_DSA(1) <= '0';
       DBB_TX1_DSA(2) <= '0';
       DBB_TX1_DSA(3) <= '0';
       DBB_TX1_DSA(4) <= '0';
       DBB_TX1_DSA(5) <= '0';
       DBB_TX2_DSA(0) <= '0';
       DBB_TX2_DSA(1) <= '0';
       DBB_TX2_DSA(2) <= '0';
       DBB_TX2_DSA(3) <= '0';
       DBB_TX2_DSA(4) <= '0';
       DBB_TX2_DSA(5) <= '0';
       DBB_RX1_DSA(0) <= '0';
       DBB_RX1_DSA(1) <= '0';
       DBB_RX1_DSA(2) <= '0';
       DBB_RX1_DSA(3) <= '0';
       DBB_RX1_DSA(4) <= '0';
       DBB_RX1_DSA(5) <= '0';
       DBB_RX2_DSA(0) <= '0';
       DBB_RX2_DSA(1) <= '0';
       DBB_RX2_DSA(2) <= '0';
       DBB_RX2_DSA(3) <= '0';
       DBB_RX2_DSA(4) <= '0';
       DBB_RX2_DSA(5) <= '0';
        
       
  
          
      -- attenuation values sent to channels based on DB_select value(0/1) and chip select value
       --DB_select - 0 is for DB-A and 1 for DB- B and chip_select determines the channel 
       elsif (DB_Select='0' and chip_select = "00") then -- attenuation value sent to first channel
        DBA_TX1_DSA(0) <= Atten(0);
        DBA_TX1_DSA(1) <= Atten(1);
        DBA_TX1_DSA(2) <= Atten(2);
        DBA_TX1_DSA(3) <= Atten(3);
        DBA_TX1_DSA(4) <= Atten(4);
        DBA_TX1_DSA(5) <= Atten(5);

        elsif (DB_Select='0' and chip_select = "01") then 
        DBA_TX2_DSA(0) <= Atten(0);
        DBA_TX2_DSA(1) <= Atten(1);
        DBA_TX2_DSA(2) <= Atten(2);
        DBA_TX2_DSA(3) <= Atten(3);
        DBA_TX2_DSA(4) <= Atten(4);
        DBA_TX2_DSA(5) <= Atten(5);
        
        elsif (DB_Select='0' and chip_select = "10") then
        DBA_RX1_DSA(0) <= Atten(0);
        DBA_RX1_DSA(1) <= Atten(1);
        DBA_RX1_DSA(2) <= Atten(2);
        DBA_RX1_DSA(3) <= Atten(3);
        DBA_RX1_DSA(4) <= Atten(4);
        DBA_RX1_DSA(5) <= Atten(5);
  
        elsif (DB_Select='0' and chip_select = "11") then
        DBA_RX2_DSA(0) <= Atten(0);
        DBA_RX2_DSA(1) <= Atten(1);
        DBA_RX2_DSA(2) <= Atten(2);
        DBA_RX2_DSA(3) <= Atten(3);
        DBA_RX2_DSA(4) <= Atten(4);
        DBA_RX2_DSA(5) <= Atten(5);
      
        -- Attenuation values being set for DB-B
        elsif (DB_Select='1' and chip_select = "00") then 
        DBB_TX1_DSA(0) <= Atten(0);
        DBB_TX1_DSA(1) <= Atten(1);
        DBB_TX1_DSA(2) <= Atten(2);
        DBB_TX1_DSA(3) <= Atten(3);
        DBB_TX1_DSA(4) <= Atten(4);
        DBB_TX1_DSA(5) <= Atten(5);
       
        elsif (DB_Select='1' and chip_select = "01") then 
        DBB_TX2_DSA(0) <= Atten(0);
        DBB_TX2_DSA(1) <= Atten(1);
        DBB_TX2_DSA(2) <= Atten(2);
        DBB_TX2_DSA(3) <= Atten(3);
        DBB_TX2_DSA(4) <= Atten(4);
        DBB_TX2_DSA(5) <= Atten(5);
 
        elsif (DB_Select='1' and chip_select = "10") then 
        DBB_RX1_DSA(0) <= Atten(0);
        DBB_RX1_DSA(1) <= Atten(1);
        DBB_RX1_DSA(2) <= Atten(2);
        DBB_RX1_DSA(3) <= Atten(3);
        DBB_RX1_DSA(4) <= Atten(4);
        DBB_RX1_DSA(5) <= Atten(5);
       
        else 
        DBB_RX2_DSA(0) <= Atten(0);
        DBB_RX2_DSA(1) <= Atten(1);
        DBB_RX2_DSA(2) <= Atten(2);
        DBB_RX2_DSA(3) <= Atten(3);
        DBB_RX2_DSA(4) <= Atten(4);
        DBB_RX2_DSA(5) <= Atten(5);

        end if;
     end if;

end process;

end Behavioral;

---Testbench Code-----------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity dsa_tb is
--  Port ( );
end dsa_tb;

architecture Behavioral of dsa_tb is

--Component Declaration for Unit Under Test (UUT)
component DSA_Worker
port(

           DB_Select : in STD_LOGIC;
           Atten : in STD_LOGIC_VECTOR ( 7 downto 0);
           enable : in STD_LOGIC;
           clk: in STD_LOGIC;
           reset: in STD_LOGIC;
           chip_select : in STD_LOGIC_VECTOR (1 downto 0);
           DBA_TX1_DSA : out STD_LOGIC_VECTOR (7 downto 0);
           DBA_TX2_DSA : out STD_LOGIC_VECTOR (7 downto 0);
           DBA_RX1_DSA : out STD_LOGIC_VECTOR (7 downto 0);
           DBA_RX2_DSA : out STD_LOGIC_VECTOR (7 downto 0);
           DBB_TX1_DSA : out STD_LOGIC_VECTOR (7 downto 0);
           DBB_TX2_DSA : out STD_LOGIC_VECTOR (7 downto 0);
           DBB_RX1_DSA : out STD_LOGIC_VECTOR (7 downto 0);
           DBB_RX2_DSA : out STD_LOGIC_VECTOR (7 downto 0));
           
    end component;
    
    --inputs 
      signal DB_Select : STD_LOGIC:= '0';
      signal Atten :  STD_LOGIC_VECTOR ( 7 downto 0):= "00000000";
      signal enable :  STD_LOGIC:='0';
      signal clk:  STD_LOGIC:='0';
      signal reset:  STD_LOGIC:='1';
      signal chip_select : STD_LOGIC_VECTOR (1 downto 0):="00";
      constant clk_period : time:=5 ns;
       
       --outputs
       
      signal    DBA_TX1_DSA : STD_LOGIC_VECTOR (7 downto 0):= "00000000";
      signal    DBA_TX2_DSA :  STD_LOGIC_VECTOR (7 downto 0):= "00000000";
      signal    DBA_RX1_DSA :  STD_LOGIC_VECTOR (7 downto 0):= "00000000";
      signal    DBA_RX2_DSA :  STD_LOGIC_VECTOR (7 downto 0):= "00000000";
      signal    DBB_TX1_DSA : STD_LOGIC_VECTOR (7 downto 0):= "00000000";
      signal    DBB_TX2_DSA :  STD_LOGIC_VECTOR (7 downto 0):= "00000000";
      signal    DBB_RX1_DSA :  STD_LOGIC_VECTOR (7 downto 0):= "00000000";
      signal    DBB_RX2_DSA :  STD_LOGIC_VECTOR (7 downto 0):= "00000000";



begin
  --Instatiate the unit under test (UUT)
  
  uut: DSA_Worker port map(
        DB_Select => DB_Select,
        Atten => Atten,
        chip_select => chip_select,
        enable => enable,
        clk => clk,
        reset => reset,
         DBA_TX1_DSA => DBA_TX1_DSA, 
         DBA_TX2_DSA => DBA_TX2_DSA ,
         DBA_RX1_DSA =>  DBA_RX1_DSA, 
         DBA_RX2_DSA =>  DBA_RX2_DSA,
         DBB_TX1_DSA =>  DBB_TX1_DSA, 
         DBB_TX2_DSA =>  DBB_TX2_DSA,
         DBB_RX1_DSA =>  DBB_RX1_DSA,
         DBB_RX2_DSA => DBB_RX2_DSA
      
     );
     
     clock_gen: process is
     
        begin
     
         clk <= '0';
         wait for clk_period/2;
         clk <= '1';
         wait for clk_period/2;
     end process clock_gen;
     
     tb : PROCESS
     BEGIN
     
         
         wait for 1 ns; 
         
         reset <= '0';
         
         wait for 10 ns; 
         
         Atten(0) <= '1';
         Atten(1) <= '1';
         Atten(2) <= '1';
         Atten(3) <= '1';
         Atten(4) <= '1';
         Atten(5) <= '1';
         Atten(6) <= '0';
         Atten(7) <= '0';
         
         chip_select <= "00"; DB_Select <='0';
          
         wait for 10 ns;
         
         
         chip_select <= "01"; DB_Select <='0';
         
         wait for 10 ns;
         
         
         
         chip_select <= "10"; DB_Select <='0';
         
         wait for 10ns;
         
         
         chip_select <= "11"; DB_Select <='0';
         
         wait for 10 ns;
         
         
         chip_select <= "00"; DB_Select <='1';
          
         wait for 10 ns;
         
         
         chip_select <= "01"; DB_Select <='1';
         
         wait for 10 ns;
         
         chip_select <= "10"; DB_Select <='1';
         
         wait for 10ns;
         
         
         chip_select <= "11"; DB_Select <='1';
         
         wait for 10 ns;
         
         
         -- stimuls goes here 
         
         end process;
end Behavioral;