I've been trying to simulate a JK-FF with gate level code, but it's not working. Any help is appreciated.
Circuit code:
module circuit1_3_c(j,k,r,cp,q,q1);
input j,k,r,cp;
output q,q1;
wire t1,t2,t3,t4;
nand(t1,t2,q);
nand(t2,t1,j,cp,t3);
nand(t3,cp,k,t4);
nand(t4,t3,t1);
nand(q,q1,t2);
nand(q1,q,t3,r);
endmodule
Testbench code:
module circuit1_3_ctest;
parameter STEP=10;
parameter HALF_STEP=5;
reg j,k,r,cp;
wire q,q1;
circuit1_3_c circ(j,k,r,cp,q,q1);
initial begin
$dumpfile("circuit1_3_c.vcd");
$dumpvars(0,circuit1_3_ctest);
$monitor("\%t: J=%b, K=%b, R=%b, Cp=%b, Q=%b, Qbar=%b", $time, j,k,r,cp,q,q1);
r<=1'b1;
cp<=1'b0;
j<=1'b0; k<=1'b0; r<=1'b1;
#STEP;
j<=1'b0; k<=1'b1; r<=1'b1;
#STEP;
j<=1'b1; k<=1'b0; r<=1'b1;
#STEP;
j<=1'b1; k<=1'b1; r<=1'b1;
#STEP;
j<=1'b0; k<=1'b0; r<=1'b1;
#STEP;
j<=1'b0; k<=1'b1; r<=1'b1;
#STEP;
j<=1'b1; k<=1'b0; r<=1'b1;
#STEP;
j<=1'b1; k<=1'b1; r<=1'b1;
#HALF_STEP
$finish;
end
always #HALF_STEP cp=~cp;
endmodule
Output. As you can see, q
and q1
are always unknown (x):
[1
You need to reset your logic properly. One way is to drive
r
as 0 at time 0. Change:to:
Output: