Vexriscv - implement ram as block ram

Question

How can I generate a Vexriscv core in a way that the generated ram is a vendor specific block ram (e.g. Intel/Altera or Xilinx)?

I tried it by using the black boxing possibility (see https://spinalhdl.github.io/SpinalDoc-RTD/v1.3.1/SpinalHDL/Sequential%20logic/memory.html) like shown in the snippet below. However, this did not workout as expected, as I assumed that passing the device information to the SpinalConfig the core generation will replace the standard memory by the vendor specific one. However, the implementation did not change.

object MuraxCustom{
  def main(args: Array[String]) {
    val hex = "../software.hex"
    val muraxConf = MuraxConfig.default(false).copy(coreFrequency = 25 MHz, onChipRamSize = 32 kB, onChipRamHexFile = hex)
    val config = SpinalConfig(device=Device(vendor = "altera", family = "Cyclone V"))
    config.addStandardMemBlackboxing(blackboxAllWhatsYouCan)
    config.generateVhdl(Murax(muraxConf))
  }
}

Any idea how I replace the ram realized as std_logic_vector as vendor specific block ram?

Answer 1

blackboxAllWhatsYouCan is currently independent of the device family your use. It will always generate using the same blockbox primitives. So no way to currently match automaticaly xilinx / altera specific memory IP

source: https://matrix.to/#/!hwePblviUiZmEwLUVw:gitter.im/$mk4C_D8BUhmN1K3ZVyliWGrfu72dQeMnHV2F2-1lE3U?via=gitter.im&via=matrix.org