Vivado Entirely Eliminating Design During Synthesis - Possibly Constraints Issue

Question

I've written some VHDL for a device that normalises random pulses with a low duty cycle and spits them out of serial.

The elaborated design looks fine. However, for some reason when I run the synthesis, it all (barring one wire) gets optimised away.

I suspect it has something to do with the constraints file because I'm getting this horrifically vague message:

[Constraints 18-5210] No constraints selected for write. Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.

My constraints file is based on the model constraints file for the CMOD A7, downloaded straight from Digilent. All I've done is change the signal names to match my top level file.

## 12 MHz Clock Signal
set_property -dict { PACKAGE_PIN L17   IOSTANDARD LVCMOS33 } [get_ports { sysclk }]; #IO_L12P_T1_MRCC_14 Sch=gclk
create_clock -add -name sys_clk_pin -period 83.33 -waveform {0 41.66} [get_ports {sysclk}];
## Buttons
set_property -dict { PACKAGE_PIN A18   IOSTANDARD LVCMOS33 } [get_ports { reset }]; 
## GPIO Pins
## Pins 15 and 16 should remain commented if using them as analog inputs
set_property -dict { PACKAGE_PIN M3    IOSTANDARD LVCMOS33 } [get_ports { din[0]  }]; #IO_L8N_T1_AD14N_35 Sch=pio[01]
set_property -dict { PACKAGE_PIN L3    IOSTANDARD LVCMOS33 } [get_ports { din[1]  }]; #IO_L8P_T1_AD14P_35 Sch=pio[02]
set_property -dict { PACKAGE_PIN A16   IOSTANDARD LVCMOS33 } [get_ports { din[2]  }]; #IO_L12P_T1_MRCC_16 Sch=pio[03]
set_property -dict { PACKAGE_PIN K3    IOSTANDARD LVCMOS33 } [get_ports { din[3]  }]; #IO_L7N_T1_AD6N_35 Sch=pio[04]
set_property -dict { PACKAGE_PIN C15   IOSTANDARD LVCMOS33 } [get_ports { din[4]  }]; #IO_L11P_T1_SRCC_16 Sch=pio[05]
set_property -dict { PACKAGE_PIN H1    IOSTANDARD LVCMOS33 } [get_ports { din[5]  }]; #IO_L3P_T0_DQS_AD5P_35 Sch=pio[06]
set_property -dict { PACKAGE_PIN A15   IOSTANDARD LVCMOS33 } [get_ports { din[6]  }]; #IO_L6N_T0_VREF_16 Sch=pio[07]
set_property -dict { PACKAGE_PIN B15   IOSTANDARD LVCMOS33 } [get_ports { din[7]  }]; #IO_L11N_T1_SRCC_16 Sch=pio[08]

set_property -dict { PACKAGE_PIN V8    IOSTANDARD LVCMOS33 } [get_ports  uart_out ]; #IO_L14N_T2_SRCC_34 Sch=pio[48]

The elaborated design even produces a schematic that looks fine.

However, the synthesised schematic is missing the bulk of my circuitry:

Any ideas what's going wrong or how I can fix this?

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Synthesis Log:

Too big to post here, but here's a gist.