What API to use for a Verilator test harness?

Question

Verilator can output SystemC or C++ classes. There is a 'Verilator' API and I can find the headers, but they are just raw classes with no documentation. Some code looks like classes that are used directly by the backend to achieve the simulation of Verilog code.

What functions can I used dependably in upgrades?

For example,

/// Flush callback for VCD waves
Verilated::flushCall()

This seems to be meant to add to my C++ codes test harness. I wrote some code to simulate a UART character,

// Time for a bit.
#define SERIAL_TIME 670 /* nS */
static sc_signal<bool> serialData;
void serialize_char(unsigned char message)
{
        // Start bit.
        if (!Verilated::gotFinish()) {
            serialData = 0;
            sc_start(SERIAL_TIME, SC_NS);
        }
        // Message byte.
        for(int  j = 0; j < 8; j++) {
            if (!Verilated::gotFinish()) {
                serialData = ((message >> j) & 1) ? !0 : 0;
                sc_start(SERIAL_TIME,SC_NS);
            }
        }
        // Stop bit.
        if (!Verilated::gotFinish()) {
            serialData = !0;
            sc_start(SERIAL_TIME,SC_NS);
        }
}    

The verilog under test is receiving data from a serial port. I want to generate different test data and signals to the module. Is this the wrong way to go about this. The API doesn't seem clear. Is it the SystemC API or is it the Verilated headers or mix and match?

Another options is to code the test harness in Verilog, but this does not provide access to a rich set of features which can be used to generate test data using external libraries and generic OS features like reading data files, etc.