I am planning to leverage hls::task in Vitis HLS to execute multiple threads concurrently within my design. While the tasks (threads) do not exhibit data dependencies, they necessitate access to off-chip memory.
According to the Vitis HLS User Manual, it is imperative to mark pointers to array arguments in the top-level function with the STABLE pragma. Additionally, any access to the underlying DRAM is unsynchronized with the task's execution process.
However, the concept of "unsynchronized access" remains somewhat ambiguous to me. I am uncertain about the exact implications and consequences of unsynchronized accesses. Could anybody provide further clarification on this matter?
Thank you