What will happen when page fault occurs in AARCH64 stage 2 translation? How can I deal with the page fault?

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I want to write a AARCH64 hypervisor. I route exceptions which happen in el1 and el2 to el2. I would like to know the specific scenarios in which a page fault occurs, such as incorrect access permissions or the memory not being mapped in the second stage. How should I handle these situations? If memory hasn't been allocated, should I use the pagetable-related interfaces in the OS to create mappings? What should I do if the page is not in memory?

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