I'm new to RISC-V and have recently started learning about it. I'm currently developing with the help of documents available on riscv.org.
While investigating Hypervisor extensions, I noticed that there is no CSR (Control and Status Register) within the Hypervisor extension specifically for setting the trap vector. There used to be a CSR called htvec, but it seems to have been omitted in the current specifications.
I tried to find out how the trap vector used during HS mode is set, and I came across information that refers to stvec.
However, I couldn't find such information in the riscv-privileged.pdf ver.20211203 document. I believe there are other CSRs in S mode that become effective during HS mode, but I'm unsure where the specifications for such behavior are documented. Does anyone have this information?
I'm planning to post this question on Stack Overflow, so please feel free to adjust the wording accordingly.
Thank you.