Yosys: how to remove useless internal wires

Question

Assume I have the following verilog:

module demo(input a, output b);
    wire c;
    assign c = ~a;
    assign b = c;
endmodule

I would like to generate a verilog where the wire c is removed.

I tried this:

read_verilog demo.v
opt
clean
write_verilog demo_opt.v

but the wire c is still there:

/* Generated by Yosys 0.24+25 (git sha1 a27a297eb, x86_64-w64-mingw32-g++ 9.2.1 -Os) */
Dumping module `\demo'.

(* cells_not_processed =  1  *)
(* src = "demo.v:1.1-10.10" *)
module demo(a, b);
  (* src = "demo.v:3.15-3.16" *)
  input a;
  wire a;
  (* src = "demo.v:4.16-4.17" *)
  output b;
  wire b;
  (* src = "demo.v:7.10-7.11" *)
  wire c;
  assign b = ~ (* src = "demo.v:8.16-8.18" *) a;
  assign c = b;
endmodule

Answer 1

Use clean -purge instead of just clean. Then, the result is:

/* Generated by Yosys 0.24+25 (git sha1 a27a297eb, x86_64-w64-mingw32-g++ 9.2.1 -Os) */
Dumping module `\demo'.

(* cells_not_processed =  1  *)
(* src = "demo.v:1.1-10.10" *)
module demo(a, b);
  (* src = "demo.v:3.15-3.16" *)
  input a;
  wire a;
  (* src = "demo.v:4.16-4.17" *)
  output b;
  wire b;
  assign b = ~ (* src = "demo.v:8.16-8.18" *) a;
endmodule