address space and wait states for a PCI device

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I was reading about how PCI bus gets to find the information about a PCI device before any transaction can take place. Please check the excerpt below.

For example, in case of a PCI memory device, how does the PCI bus/controller get to know about the size of the memory device like if it is one-Megabyte and the address range used by it? I think one MB memory needs 2^20 addresses. Is this information stored in some sort of register(s)?

Likewise, how does a PCI bus or controller gets to know about the wait states used by a memory device for read and write operation? For example, the PCI memory might need 3 wait cycles for the read operation. Is this information stored in some sort of register(s)?

How does PCI determines the size of memory

Source: PCI Bus Demystified by Abbott, 2nd ed, Pg. 89

I went to through a chapter of the mentioned book but couldn't really get the answer. I'm trying to understand it at a basic level and I'm a beginner.

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