According to the source of the Wikipedia page on the Knight's Landing chip, it has Airmont cores. According to this page, those cores support SSE4.2 instructions, that is, SIMD instructions on SIMD registers. Is that really the case? If so, what's the actual maximum width of, say, arithmetic instructions on these Airmont cores? (In terms of total width of the register, or width of a lane or element within the register x number of lanes).
Do the Airmont cores on Knight's Landing Xeon Phi's support SIMD instructions?
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Each core has two vector units which, as well as 512 bit AVX-512, also support all SSE variants (at 128 bits of course), and likewise AVX/AVX2 (at 256 bits).
The 512 bit ZMM registers can be used as 256 bit AVX (YMM) registers or 128 bit SSE (XMM) registers. If you want to do anything with 8 or 16 bit vector elements though you are limited to SSE/AVX2, since AVX-512BW support is lacking.