Question

The problem with AyncFIFO with two clock sources written in Chisel 5.0

score 101 · Answer 1 · 2025-01-02 20:59:06

101

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The problem with AyncFIFO with two clock sources written in Chisel 5.0

Published on 02 January 2025 at 20:59

score 79 · Answer 2 · 2025-01-02 20:50:32

79

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Expecting a SInt value from a Wire, in Chisel

Published on 02 January 2025 at 20:50

score 241 · Answer 3 · 2025-01-02 20:52:54

241

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Providing a simulation model for a chisel blackbox

Published on 02 January 2025 at 20:52

score 447 · Answer 4 · 2025-01-02 20:47:52

447

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ChiselTest - expect a bit value in a UInt

Published on 02 January 2025 at 20:47

score 110 · Answer 5 · 2025-01-02 20:56:57

110

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Why is this local var not set correctly according to ChiselTest

Published on 02 January 2025 at 20:56

score 449 · Answer 6 · 2025-01-06 15:41:08

449

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Debugging module internals in Chisel

Published on 06 January 2025 at 15:41

score 190 · Answer 7 · 2025-01-02 20:56:56

190

Views

Testing Chisel object functions that use hardware constructs

Published on 02 January 2025 at 20:56

score 802 · Answer 8 · 2025-01-02 20:46:44

802

Views

Why Bool(true) != Bool(true) in chisel3?

Published on 02 January 2025 at 20:46

score 180 · Answer 9 · 2025-01-04 11:13:49

180

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What the purpose of `initSource`, `initSink` or `setSinkClock` in chiseltest test harness?

Published on 04 January 2025 at 11:13

score 139 · Answer 10 · 2025-01-02 21:00:34

139

Views

Why do poked values change on last clock cycle in chiseltest, thus failing asserts?

Published on 02 January 2025 at 21:00

score 164 · Answer 11 · 2025-01-02 22:24:46

Exception in thread "main" chisel3.package$ChiselException: Unable to locate the elaborated circuit, did chisel3.stage.phases.Elaborate run correctly

score 286 · Answer 12 · 2025-01-02 20:46:43

286

Views

method <init>()V not found in chisel test

Published on 02 January 2025 at 20:46

score 576 · Answer 13 · 2025-01-02 20:56:54

576

Views

In chisel 3, how to initialize memory test code with text file

Published on 02 January 2025 at 20:56

score 163 · Answer 14 · 2025-01-02 20:56:54

163

Views

Chisel queue module test results don't match what i expected

Published on 02 January 2025 at 20:56

score 119 · Answer 15 · 2025-01-02 20:54:18

119

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How to overcome fixedpoint division problem in chisel3?

Published on 02 January 2025 at 20:54

score 289 · Answer 16 · 2025-01-02 20:46:00

289

Views

chisel 5.0.0-RC1 and chiseltest

Published on 02 January 2025 at 20:46

score 121 · Answer 17 · 2025-01-02 20:56:53

121

Views

Serializer in Chisel: Register printf dont seem to make sense

Published on 02 January 2025 at 20:56

score 459 · Answer 18 · 2025-01-02 20:50:04

459

Views

How to create a Vec literal from a Seq[Bool]

Published on 02 January 2025 at 20:50

score 388 · Answer 19 · 2025-01-02 20:46:14

388

Views

How can I test a Chisel3 BlackBox?

Published on 02 January 2025 at 20:46

score 22 · Answer 20 · 2025-01-02 21:01:15

22

Views

An error occured while testing Queue. 'FlitTypes' must be hardware, not a bare Chisel type

Published on 02 January 2025 at 21:01

List Question

The problem with AyncFIFO with two clock sources written in Chisel 5.0

Expecting a SInt value from a Wire, in Chisel

Providing a simulation model for a chisel blackbox

ChiselTest - expect a bit value in a UInt

Why is this local var not set correctly according to ChiselTest

Debugging module internals in Chisel

Testing Chisel object functions that use hardware constructs

Why Bool(true) != Bool(true) in chisel3?

What the purpose of `initSource`, `initSink` or `setSinkClock` in chiseltest test harness?

Why do poked values change on last clock cycle in chiseltest, thus failing asserts?

Exception in thread "main" chisel3.package$ChiselException: Unable to locate the elaborated circuit, did chisel3.stage.phases.Elaborate run correctly

method <init>()V not found in chisel test

In chisel 3, how to initialize memory test code with text file

Chisel queue module test results don't match what i expected

How to overcome fixedpoint division problem in chisel3?

chisel 5.0.0-RC1 and chiseltest

Serializer in Chisel: Register printf dont seem to make sense

How to create a Vec literal from a Seq[Bool]

How can I test a Chisel3 BlackBox?

An error occured while testing Queue. 'FlitTypes' must be hardware, not a bare Chisel type

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