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15
89
Views

How to convert a deprecated low Firrtl Transform to the Dependency API

Published on
#chisel #firrtl
223
Views

Chisel/FIRRTL DefnameDifferentPortsException

Published on
#chisel #firrtl
553
Views

Differences between LazyModule and LazyModuleImp

Published on
#riscv #chisel #rocket-chip #firrtl
97
Views

Bundle using Mux

Published on
#chisel #firrtl
593
Views

False "Combinational loop detected"

Published on
#scala #chisel #firrtl
132
Views

what do "cmem", "infer", and "mport" mean?

Published on
#chisel #firrtl
114
Views

how to get a critical path / bottleneck analysis of FIRRTL code?

Published on
#riscv #chisel #firrtl
292
Views

Chisel 3.4.2 syncmem and a black box. No memory replacement with --repl-seq-mem option

Published on
#chisel #firrtl
140
Views

How to emitVerilog from Firrtl with annotations

Published on
#annotations #verilog #chisel #firrtl
144
Views

Exception in thread "main" chisel3.package$ChiselException: Unable to locate the elaborated circuit, did chisel3.stage.phases.Elaborate run correctly

Published on
#chisel #chiseltest #firrtl
156
Views

what is the best practice to initialize a FIRRTL memory?

Published on
#chisel #firrtl
88
Views

what is the idiomatic way to update *part* of a memory element in FIRRTL? this comes up when updating one entry of a line in a cache

Published on
#chisel #firrtl
186
Views

Initializing IO with a bundle in Chisel 3.5

Published on
#chisel #firrtl
49
Views

How to move sram to top hierarchy in Chisel3/Firrtl

Published on
#memory #hierarchy #chisel #synthesize #firrtl
222
Views

Chisel: fail to generate verilog while writing a simple combinational logic

Published on
#scala #verilog #chisel #firrtl

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