I want to know the number of TLB misses that resulted in memory (DRAM) access. In "Intel(R) Xeon(R) W-2104" system, I can see perf counters like "dtlb_load_misses.miss_causes_a_walk" and "dtlb_store_misses.miss_causes_a_walk" which gives count of page table walks (even though these counts are higher than what I expected), now is there a direct or indirect way to correlate these counts with some other perf event to approximate address translation memory accesses?
I was thinking of correlating with LLC misses as it corresponds to memory accesses, but I could not finalize a strategy to filter out translation misses from LLC misses.