How do I disable assertions when signals are unknown?

Question

I'm trying to understand a assertion in a MUX sample module.

I would like to check the interference between SEL1, SEL2 and SEL3 signals, So I declared as the below,

always @(posedge CLOCK)
  assert (SEL1 == 1 && SEL2 ==0 && SEL3 == 0);

I got the some assertion fail about SELx. It make sense, and I will fix it, but I didn't understand the first fail:

xmsim: *E,ASRTST (./testbench.sv,31): (time 5 NS) Assertion T_MUX.MUX1.__assert_1 has failed 
Starting 1st set of test vectors.

I think that fail does not come from SELx, it comes from known value. As I know known. the unknown value is inevitable, even when we initiate the system, before reset, system's some ports have the known state.

How do I correctly make a assertion checker with unknown initial state?

For your understand I have added https://edaplayground.com/x/LLYS

module MUX       
(                
  input wire       CLOCK  ,
  input wire [3:0] IP1    ,
  input wire [3:0] IP2    ,
  input wire [3:0] IP3    ,
  input wire       SEL1   ,
  input wire       SEL2   ,
  input wire       SEL3   ,
  output reg [3:0] MUX_OP
) ;              
                 
always @(posedge CLOCK)
  if (SEL1 == 1) 
    MUX_OP <= IP1 ;
  else if (SEL2 == 1)
    MUX_OP <= IP2 ;
  else if (SEL3 == 1)
    MUX_OP <= IP3 ;                     

always @(posedge CLOCK)
  assert (SEL1 == 1 && SEL2 ==0 && SEL3 == 0);
endmodule

Answer 1

At time 5ns, all 3 SEL signals are unknown (x) because the MUX inputs are not driven with a known value until time 7ns (2ns after the 1st clock edge).

If you want to disable the assertion whenever any of the SEL signals has an unknown value, you can use the $isunknown system function:

always @(posedge CLOCK) begin
    if (!$isunknown({SEL1, SEL2, SEL3})) begin
        assert ( (SEL1 === 1) && (SEL2 === 0) && (SEL3 === 0) );
    end
end

Refer to IEEE Std 1800-2017, section 20.9 Bit vector system functions.

This checks if any SEL signal is x or z. It checks for the duration of the simulation, not just the 1st clock event.

There is no assert fail at time 5ns on the updated EDA Playground.