How to connect 2 ports(input) to same wire in verilog

Question

Instantiate the following module connecting ports by name. The output of the module should be connected to wire S, port B should connect to wire T, and port C should also connect to wire T.

my_module(output A, input B, input C);

How can I write Verilog code for this?

Answer 1

in verilog when connections are expressed by associating wires with ports or other variables. An example of instance connections follows. Wire T (input to the top module) is connected to ports B and C of the my_module from your example.

module top(output S, input T);
   my_module mminst(.A(S), .B(T), .C(T));
endmodule