invalid module instantiation systemverilog

Question

I am trying to run this code in eda playground but I am getting following errors:

module array_redu(); 
  byte b[] = { 1, 2, 3, 4 }; 
  int sum,product,b_xor;
  initial
    begin 
      sum =b.sum ;  // y becomes 10 => 1 + 2 + 3 + 4
      product =b.product ;  // y becomes 24 => 1 * 2 * 3 * 4
      b_xor=b.xor with (item+ 4 );  // y becomes 12 => 5 ^ 6 ^ 7 ^8 
      $display(" Sum is %0d, product is %0d, xor is  %0b",sum,product,b_xor)
      end
endmodule

I am getting following errors:

design.sv:2: syntax error
design.sv:2: error: Invalid module instantiation
design.sv:3: syntax error
design.sv:3: error: Invalid module instantiation
design.sv:8: syntax error
design.sv:8: error: malformed statement
design.sv:10: syntax error

Answer 1

I simulated your code using Aldec Riviera Pro on EDA Playground. There was only 1 error: you are missing a semi-colon from the end of the line with $display.