Is there a flag register in the Power ISA?

Question

Is there a flag register in the Power ISA, similar to EFLAGS in the x86 machines? It could have some other name, for example it could be called "Status Register" or something of that kind, but its purpose would be saving some general attributes of the last instruction execution, for example overflow and carriage flags in arithmetic operations or the result of comparision two integer numbers before making a conditional jump. I know, SPARC and ARM processors have such a register while MIPS and RISC-V ISAs are deprived of it. What's about another popular architecture - Power (from PowerPC to Power10)? What approach is adopted in this architecture, concerning flags and this register? How can one check for an overflow when say adding two unsigned 64-bit integer numbers? How is comparing two integer numbers and conditional branching on the results of this comparision organized in this processor on the ISA level?

Could anybody enumerate all popular well-known general purpose RISC architectures and notify which ones have a flag (or status) registers and which ones don't?

Answer 1

They are called the Condition Register(s) on PowerPC.

2.3.1 Condition Register

The Condition Register (CR) is a 32-bit register which reflects the result of certain operations, and provides a mechanism for testing (and branching).

The bits in the Condition Register are grouped into eight 4-bit fields, named CR Field 0 (CR0), ..., CR Field 7 (CR7), which are set in one of the following ways.

The Power architectures have multiple sets of flags: 8 of 4-bit condition codes, CR0-CR7, held collectively in one 32-bit condition register — when you use compare instructions and branch instruction, you choose which 4-bit flags field to target.  Some instructions implicitly target CR0 or CR1.