Although I don't read Itanium assembly, and I don't claim to understand its memory model, I have noticed something very strange and apparently contradictory in one proposed mapping of C/C++ atomics to Itanium.
In C/C++11 mappings to processors the proposed implementation of atomics on Itanium suggests no acquire or release fences:
Consume Fence: <ignore>
Acquire Fence: <ignore>
Release Fence: <ignore>
Acq_Rel Fence: <ignore>
(What is a consume fence anyway?)
And indeed in that proposal the relaxed atomic loads and stores are never relaxed:
Load Relaxed: ld.acq
Load Consume: ld.acq
Load Acquire: ld.acq
...
We see that all relaxed simple (not RMW) operations are already Acq_Rel in these mappings. But looking at RMW operations with see that the relaxed and non-relaxed operations are different:
Cmpxchg Release: cmpxchg.rel
Cmpxchg AcqRel: cmpxchg.rel; mf
Unless the Cmpxchg AcqRel implementation has gratuitous mf (unlikely), it means the acquire behavior is not automatic in cmpxchg.rel.
Shouldn't a relaxed, release-only RMW operation followed by an acquire fence provide at least the guarantees of acq_rel RMW? If so, doesn't that show the proposal is defective?