iverilog error: syntax in assignment statement l-value

Question

I'm new to SystemVerilog, and I use Icarus Verilog. I'm trying to design a simple FSM to practise, but I keep getting this error:

error: syntax in assignment statement l-value

module primoex (input logic clk, reset, x,
               output logic y);
               
    enum reg [1:0] {S0, S1, S2} stati;
    reg [1:0] stato, statoprox;
     

     always_ff@(posedge clk, posedge reset) 
      if(reset) stato = S0; 
      else stato <= statoprox;

    always_comb 
    case (stato)
        S0: statoprox = x? S1 : S0;
        S1: statoprox = x? S2 : S0;
        S2: statoprox = x? S2 : S0;
        default= S0;
    endcase

    
    assign y = S1 & ~S0; 

endmodule

Answer 1

In a case statement, the default keyword is used in place of other case item values; you can not assign a value to it. You still need to use the signal name that you are assigning.

Change:

    default= S0;

to:

    default statoprox = S0;

This code compiles on edaplayground on several simulators. You can sign up for a free account.

It does not compile on Icarus there, but you may have a different version. I see different compile errors from the one you reported. Keep in mind that Icarus does not support all SystemVerilog features.