ShiftRegister Verilog HDL Output giving xxxxxxx

Question

I'm Trying to make a 64-bit shift register in Verilog HDL. When I try the code in the testbench, I just get xxxxxx as the output till all the bits have been shifted. I don't know what the problem is. Here Is my code with the testbench and the result:

module ShiftRegister (shift_out, clk, shift_in); //module ports
  parameter n = 64; //Parameter n declared to store 64
  input [n-1:0] shift_in; //64-bit input shift_in
  input clk; //Input clock
  output [n-1:0] shift_out; //64-bit output shift_out
  reg [n-1:0] ff; //64-bit flipflop
  assign shift_out = ff [n-1:0]; //give the output of the 64th bit
  //The operation of verilog: 
   always @ (posedge clk) //Always at the rising edge of the clock
   begin
     ff <= ff << 1;  //Shift bits to the left by 1
     ff[0] <= shift_in; //Take the input bits and give it to the first flipflop
     end
endmodule //ShiftRegister module

///Testbench\\\ 
module ShiftRegister_tb; //Module shiftRegister_tb
   parameter n = 64; //Parameter n declared to store 64
   reg [n-1:0] shift_in; //64-bit register input shift_in
   reg clk, rst; //register clock
   wire [n-1:0] shift_out; //64-bit wire output shift_out
   ShiftRegister DUT(shift_out, clk, shift_in); //Calling the module
  initial
    begin
    clk = 0; //clock = 0 initally
    shift_in = 64'd34645767785344; //Random decimal number to test the code 
    #100;
   end
 always #50 clk =~clk; //invert the clock input after 50ps
endmodule //ShiftRegister testbench

Answer 1

You declare ff as a reg, and the default value of a reg is x. Before the 1st posedge of the clock, all 64 bits of ff are x (unknown). After the 1st posedge of the clock, ff[0] becomes 0 because shift_in[0] is 0. And so on, until you reach 64 clocks, then all ff bits are 0. shift_out just follows ff.

Typically, your design would also have a reset signal. If you had one, you could assert reset at the start, and assign ff to 0 during reset. Here is what is looks like with a reset:

module ShiftRegister (shift_out, clk, shift_in, rst); //module ports
    parameter n = 64; //Parameter n declared to store 64
    input rst;
    input [n-1:0] shift_in; //64-bit input shift_in
    input clk; //Input clock
    output [n-1:0] shift_out; //64-bit output shift_out
    reg [n-1:0] ff; //64-bit flipflop
    assign shift_out = ff [n-1:0]; //give the output of the 64th bit

    always @ (posedge clk or posedge rst) //Always at the rising edge of the clock
    begin
        if (rst) begin
            ff <= 0;
        end else begin
            ff <= ff << 1;  //Shift bits to the left by 1
            ff[0] <= shift_in; //Take the input bits and give it to the first flipflop
        end
    end
endmodule

module ShiftRegister_tb; //Module shiftRegister_tb
    parameter n = 64; //Parameter n declared to store 64
    reg [n-1:0] shift_in; //64-bit register input shift_in
    reg clk, rst; //register clock
    wire [n-1:0] shift_out; //64-bit wire output shift_out
    ShiftRegister DUT(shift_out, clk, shift_in,rst); //Calling the module
    initial
    begin
        clk = 0; //clock = 0 initally
        rst = 1;
        shift_in = 64'd34645767785344; //Random decimal number to test the code 
        #100;
        rst = 0;
        #50_000 $finish;
    end
    always #50 clk =~clk; //invert the clock input after 50ps
endmodule