A simple question: under which FPCR configuration ARM FP instructions conform to IEEE 754-2008?
I suppose that IEEE 754-2008-conformirng FPCR configuration is:
- AHP (Alternative half-precision control bit): 0
- DN (Default NaN use for NaN propagation): 0
- FZ (Flushing denormalized numbers to zero control bit): 0
- RMode (Rounding Mode control field): 0 (Round to Nearest (RN) mode)
- Stride (This field has no function in AArch64 state): x (don't care)
- FZ16 (Flushing denormalized numbers to zero control bit on half-precision): 0
- Len (This field has no function in AArch64 state): x (don't care)
- IDE (Input Denormal floating-point exception trap enable): 0
- EBF (Controls the numeric behaviors of BFloat16 dot product calculations performed by the BFDOT, BFMMLA, BFMOPA, and BFMOPS instructions): x (don't care)
- IXE (Inexact floating-point exception trap enable): x (don't care)
- UFE (Underflow floating-point exception trap enable): x (don't care)
- OFE (Overflow floating-point exception trap enable): x (don't care)
- DZE (Divide by Zero floating-point exception trap enable): x (don't care)
- IOE (Invalid Operation floating-point exception trap enable): x (don't care)
- NEP (Controls how the output elements other than the lowest element of the vector are determined for Advanced SIMD scalar instructions): 0
- AH (Alternate Handling. Controls alternate handling of floating-point numbers): 0
- FIZ (Flush Inputs to Zero. Controls whether single-precision, double-precision and BFloat16 input operands that are denormalized numbers are flushed to zero): 0
Is that correct?