Does FPU typically have (direct) access to status register?

Question

Context: in case of a floating-point exception, usually an appropriate bit is set in a status register.

Here is an example taken from ARM preudocode:

FPProcessException(FPExc exception, FPCRType fpcr)
...
    elsif UsingAArch32() then
        // Set the cumulative exception bit
        FPSCR<cumul> = '1';
    else
        // Set the cumulative exception bit
        FPSR<cumul> = '1';

A simple question: who exactly does this bit setting: FPU itself or some other component (which one)?

In other words: does FPU typically have (direct) access to status register?

Any ideas / thoughts / experience?

Reason of the question: knowledge of hardware design in order to achieve better decomposition while expressing instruction set architecture (ISA) semantics.