Why gcc is not using S16-S31 registers of Cortex M7?

Question

Cortex M7 with the FPv5 extension has 32 single precision floating point registers (or 16 double precision registers). GCC version 10.3.1 20210824 (release) (GNU Arm Embedded Toolchain 10.3-2021.10) seems to generate code that uses only the first 16 single precision registers. Why is it so? Is there a way to make it use the other half, when only single precision math is used?

I'm compiling with -mcpu=cortex-m7 -mfpu=fpv5-sp-d16 -mfp16-format=ieee

Answer 1

Ok, I was actually wrong, gcc does emit code that uses these S16-S31 registers with these flags. Just not in the function I was focused on. Apparently it decided they are of no use there. Optimization info does not cover such details, it seems. I guess the "-d16" part of the flag refers to 16 double precision registers.