Would like seek for help on the following Verilog Shift Register Code. The following code was given to me and my task is to convert that into a schematic form.
module shift_register(
output reg [9:0] out_q,
input clk,
input reset,
input test,
input in_cg,
input in_sr);
always @(posedge clk or negedge reset) begin
if (reset ==0) begin
out_q <= 10'd0;
end
else if (test == 0) begin
out_q <= {out_q[8:0], in_cg};
end
else begin
out_q<={out_q[8:0],in_sr};
end
end //end always
endmodule //endmodule
I had draft my schematic as attached as ShiftRegister here. Someone please help to verify is this the right schematic manually "synthesize" from the Verilog RTL code? Thanks.
You should replace "end else if" to "end else begin if"