What is the difference between using a 'constant' and using a number in vhdl

Question

As part of adaptations to an existing large design on Artix-7 FPGA, I implemented a simple counting mechanism, something similar to "Archticture with 'constant' ", so that in the future, I can just change the value of the constant and not worry too much about where it is used.

However, it led to several timing failures and I went back to the normal way to increment a counter, by adding a 1, which resolved the timing failures. Here are the entity and the 2 architectures that I tried synthesizing in Vivado 2016.4 tool. But the Project Summary tab in Vivado shows no resources except IO was used.! So my question is, does declaring constants in VHDL result in more hardware than usual? What is the difference between the 2 implementations?

Entity

entity counter is
Port(
      i_clk : in std_logic;
      i_rst : in std_logic;
      o_cnt : out std_logic_vector(7 downto 0)
    );
end counter;

Architecture with 'constant'

architecture Behavioral of counter is
signal s_cnt : unsigned(7 downto 0) := (others => '0');
signal s_max : unsigned(7 downto 0) := (others => '1');

constant c_INCR : unsigned(3 downto 0) := x"1";
begin
process (i_clk) begin
    if rising_edge(i_clk) then
        if i_rst = '1' then
            s_cnt <= (others => '0');
        else
            o_cnt <= std_logic_vector(s_cnt);
            if s_cnt = s_max then
                s_cnt <= (others => '0');
            else
                s_cnt <= s_cnt + c_INCR;
            end if;
        end if;
    end if;
end process;

end Behavioral;

Architecture with '+1'

architecture Behavioral of counter is
signal s_cnt : unsigned(7 downto 0) := (others => '0');
signal s_max : unsigned(7 downto 0) := (others => '1');

begin
process (i_clk) begin
    if rising_edge(i_clk) then
        if i_rst = '1' then
            s_cnt <= (others => '0');
        else
            o_cnt <= std_logic_vector(s_cnt);
            if s_cnt = s_max then
                s_cnt <= (others => '0');
            else
                s_cnt <= s_cnt + 1;
            end if;
        end if;
    end if;
end process;

end Behavioral;