Why is my 32x32 register array not updating the output?

Question

I'm having some issues with this code I made. The function is to save whatever is on input d to an output q, which can be any of the 32 registers that have been declared on the module. This may be available at any moment, so that's why the output port is 32x32 long.

I created the testbench and everything compiles, but in waveform, I'm having only x to the output. What am I doing wrong?

This is my module:

module register32_32 
#(parameter BUS_WIDTH = 32)
    (input [5:0]sel,
    input [BUS_WIDTH - 1:0] d,
    input clk,
    output reg [31:0][BUS_WIDTH - 1:0]q
);

    always@(posedge clk) begin
        
        q[sel] <= d; 
        
    end

endmodule

And this is my testbench; everything is simulated in ModelSim.

The expected output is meant to be ffffffff in q[1] and then eeeeeeee in q[2]:

`timescale 1ns/1ns
module registrosTB;
reg clk = 0;
reg [31:0]d;
reg [4:0] sel;
wire [31:0][31:0] q;

registro4a8 DUT (
.clk(clk),
.d(d),
.sel(sel),
.q(q)
);

always clk = #5 ~clk;
initial begin
    sel = 1;
    d = 32'hffffffff;
    #10;
    sel = 2;
    d = 32'heeeeeeee;
    #10;
end

endmodule

Answer 1

You need to fix the module instance in the testbench. Change:

registro4a8 DUT (

to:

register32_32 DUT (

When I run a simulation and dump waveforms, I see the expected values on q[1] and q[2]. All the other q values have X's because you did not select them in the testbench. In the waveform window, I needed to expand the 32x32 q array to see individual 32-bit values. Otherwise, the full 32x32 signal looks like it only has X's. In the waves below, I just show 0-7.

Also, the simulators I used generated a compile warning like this:

.sel(sel),
       |
xmelab: *W,CUVMPW : port sizes differ in port connection(5/6) for the instance(registrosTB) .

This does not affect your results, but you should fix it:

reg [5:0] sel;