4 input nand gate using 2 input nand

Question

Im trying to create a 4 input nand using only 2 input nand and this one isnt giving me the right simulation.

entity NAND4_YourName is
    Port ( A, B, C, D : in STD_LOGIC;
           Y : out STD_LOGIC );
end NAND4_YourName;

architecture Behavioral of NAND4_YourName is
    signal AB_NAND, CD_NAND: STD_LOGIC;
begin
    -- First stage: NAND the pairs of inputs
    AB_NAND <= A nand B;
    CD_NAND <= C nand D;
    
    -- Second stage: NAND the results of the first stage together
    Y <= AB_NAND nand CD_NAND;
end Behavioral;

Answer 1

Your subexpression nand(nand(A, B), nand(C, D)) is not equivalent to nand(A, B, C, D). You can cascade AND gates and get a bigger AND gate, but you can’t cascade NAND gates to get a bigger NAND gate because of the inverted output - it changes the intermediate values.

What you need to do is get the AND of all four signals, then invert it. To make an AND gate of NAND gates you just NAND the inputs and then feed the output NAND into both inputs of another NAND, which inverts the output.

architecture Behavioral of NAND4_YourName is
    signal AB_NAND, CD_NAND, AB_AND, CD_AND: STD_LOGIC;
begin
    -- First stage: NAND the pairs of inputs
    AB_NAND <= A nand B;
    CD_NAND <= C nand D;

    -- Second stange: invert the NAND outputs to make them AND
    AB_AND <= AB_NAND nand AB_NAND;
    CD_AND <= CD_NAND nand CD_NAND;
    
    -- Third stage: NAND the results of the second stage together
    Y <= AB_AND nand CD_AND;
end Behavioral;

^{FD I haven't written any VHDL so this may be syntactically invalid. But you get the idea, right?}