VHDL Finite State Machine not transitioning correctly based on external signal

Question

I'm currently working on a VHDL project involving a finite state machine (FSM) that transitions through three states (STATE_0, STATE_1, and STATE_2) based on an external signal T. Each state should wait for a certain number of pulses from T before transitioning to the next state.

The behavior I'm expecting is as follows:

When in STATE_0, the FSM should transition to STATE_1 after receiving 2 pulses from T. When in STATE_1, it should transition to STATE_2 after receiving 4 pulses. When in STATE_2, it should transition back to STATE_0 after receiving 6 pulses. However, my FSM implementation doesn't seem to be behaving correctly. It's not transitioning states as expected, and I suspect there might be issues with how I'm handling the counter and state transitions.

I've provided the VHDL code below, along with a waveform file from my simulation (used Quartus II 9.0 web edition). The code compiles correctly.

Take into account I am a complete beginner in VHDL and this is my first question in Stack Overflow, so any feedback on how to better the way I ask questions will be highly appreciated.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity STLC is
Port (
clk, T : in STD_LOGIC;
state_out : out STD_LOGIC_VECTOR(1 downto 0)
);
end entity STLC;

architecture Behavioral of STLC is
type state_type is (STATE_0, STATE_1, STATE_2);
signal current_state, next_state : state_type;
signal counter : integer range 0 to 63 := 0; -- Inner counter to track state durations
signal B : integer range 0 to 63 := 0;

begin

    state_transition_process: process(current_state, counter)
    begin
        case current_state is
                when STATE_0 =>
                    if counter - B > 2 then
                        next_state <= STATE_1;
                        B <= counter;  -- Reset counter
                    else 
                        next_state <= STATE_0;
                    end if;
                when STATE_1 =>
                    if counter - B > 4 then
                        next_state <= STATE_2;
                        B <= counter;  -- Reset counter
                    else 
                        next_state <= STATE_1;
                    end if;
                when STATE_2 =>
                    if counter - B > 6 then
                        next_state <= STATE_0;
                        B <= counter;  -- Reset counter
                    else 
                        next_state <= STATE_2;
                    end if;                    
                when others =>
                    next_state <= STATE_0;
            end case;
    end process;
    
    -- Output logic
    output_logic: process (current_state)
    begin
        case current_state is
            when STATE_0 =>
                state_out <= "00";
            when STATE_1 =>
                state_out <= "01";
            when STATE_2 =>
                state_out <= "10";
            when others =>
                state_out <= "00";  -- Default state
        end case;
    end process output_logic;
    
    -- State flip-flop
    state_ff: process (clk)
    begin
        if clk'event and clk='1' then
            current_state <= next_state;
            if T='1' then
                counter <= counter + 1;  -- Increment counter on T signal activation
            end if;
        end if;
    end process state_ff;

end architecture Behavioral;

Updated simulation after adding B to sensitivity list

Could someone please review my code and provide guidance on what might be causing this issue? Any help would be greatly appreciated. Thank you!

I've implemented a finite state machine in VHDL, specifying the transitions between states based on the number of pulses received from the external signal T. I've coded the logic for each state transition and initialized counters to track the number of pulses. However, despite my efforts, the FSM isn't transitioning states as expected. I expected the FSM to transition from STATE_0 to STATE_1 after 2 pulses, from STATE_1 to STATE_2 after 4 pulses, and from STATE_2 back to STATE_0 after 6 pulses.