Im trying to buil a “N” bit parameterizable accumulator based in an adder and in a register, both parameterizable

Question

I built an accumulator based in an adder and an a register( all paremeterizable). when i use the default value that i specified(N=8) in all the codes it works but when i try to change the N value to N=4 it doesnt work. I tried understanding why but i feel like the code is right so why is it when i try to use other N value it doesnt wotk?

AdderN code:

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;

entity AdderN is 
    generic (N : positive :=4);      --valor de bits se n for introduzido nenhum N
    port( operand0,operand1 : in std_logic_vector(N-1 downto 0);
            result : out std_logic_vector(N-1 downto 0));
            
end AdderN;

architecture Behavioral of AdderN is


signal s_op0, s_op1, s_res : unsigned(N downto 0);

begin
    s_op0<='0' & unsigned(operand0);
    s_op1<= '0' & unsigned(operand1);
    s_res<= s_op0 + s_op1;
    
    result<= std_logic_vector(s_res(N-1 downto 0));
    
end Behavioral;

RegN code:

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;

entity RegN is 
    generic(N: positive :=4);
    port(dataIn: in std_logic_vector(N-1 downto 0);
          reset: in std_logic;
          clk : in std_logic;
          enable : in std_logic;
          dataOut: out std_logic_vector(N-1 downto 0));
end RegN;

architecture Behavioral of RegN is

begin
    process(reset, clk) 
    begin 
        if (reset='1') then
            dataOut<=(others=>'0');
        elsif (rising_edge(clk)) then 
            if (enable = '1') then
                dataOut <= dataIn;              
            end if;         
        end if;     
    end process;        
end architecture Behavioral;
            

AccN code:

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;

entity AccN is 
    generic(N : positive := 4);
    port(dataIn: in std_logic_vector(N-1 downto 0);
          reset: in std_logic;
          clk: in std_logic;
          enable: in std_logic;
          dataOut: out std_logic_vector(N-1 downto 0));
          
end AccN;

architecture Structural of AccN is
    signal s_adderOut, s_regOut,s_result : std_logic_vector(N-1 downto 0);
begin
    
    addern: entity work.AdderN(Behavioral)
        port map(operand0=>dataIn,
                    operand1=>s_regOut,
                    result=>s_adderOut);
    reg: entity work.RegN(Behavioral)
        port map(dataIn=>s_adderOut,
                    enable=>enable,
                    clk=>clk,
                    reset=>reset,
                    dataOut=>s_result);
        dataOut<=s_result;
end architecture Structural;

I tried changing the default value to N=4 but when i try to change it it gives me the same error:

Error (10344): VHDL expression error at AccN.vhd(20): expression has 4 elements, but must have 8 elements Error (10324): VHDL Expression error at AccN.vhd(21): expression ""UUUU"" has 4 elements ; expected 8 elements. Error (10344): VHDL expression error at AccN.vhd(22): expression has 4 elements, but must have 8 elements Error (10346): VHDL error at AccN.vhd(19): formal port or parameter "operand0" must have actual or default value Error (10346): VHDL error at AccN.vhd(19): formal port or parameter "operand1" must have actual or default value Error (10344): VHDL expression error at AccN.vhd(22): expression has 8 elements, but must have 4 elements