I'm trying to study for an exam and I've been searching for any videos or images or pages explaining the time diagram for the D-Latch that involves the preset and clear. I'm finding a lot of results for the D flip-flop but not just the D-latch. Here's what the diagram looks like for the D flip-flop, that was fortunately labelled as a flip-flop so I knew which one it is. I need to study the same thing but for the D-latch too, and I need the preset and clear to be in the diagram, I'm finding more basic D, Q, and Clock time diagrams for the D-latch but not one like this flip-flop diagram that has D, Q, Clock, Preset, and Clear.
Here is an example of a time diagram for D-latch that has both preset & clear inputs:
The important bits to take note of for the D-latch are that it is a level-triggering device as opposed to an edge-triggering device (like D flip-flops). That simply means the D-latch can change states ONLY while the clock input is HIGH and otherwise maintains the state it had the moment the clock changed states to LOW. Preset and Clear are asynchronous inputs, meaning they can affect the output of the D-latch regardless of the clock input. If Preset is LOW, then the output of the latch is always HIGH, and if Clear is low then the output is always LOW. If there is ever a case where both Preset and Clear are both activated, Q and Q' both go to the same state simultaneously giving an invalid state as the output.