Question

Intel TSX: xbegin always returns 0

score 106 · Answer 1 · 2023-09-07T06:54:10.573000

106

Views

Intel TSX: xbegin always returns 0

Published on 07 September 2023 at 06:54

score 63 · Answer 2 · 2023-04-09T10:00:07.017000

63

Views

Intel TSX programming environement

Published on 09 April 2023 at 10:00

score 151 · Answer 3 · 2023-04-06T08:43:52.880000

151

Views

How to know Intel TSX is currently used by other process?

Published on 06 April 2023 at 08:43

score 1.1k · Answer 4 · 2022-12-12T01:30:50.157000

1.1k

Views

How to enable Intel TSX in i7-7700 cpu?

Published on 12 December 2022 at 01:30

score 397 · Answer 5 · 2022-08-02T15:37:40.840000

397

Views

Understanding ARM Transactional Memory Extensions

Published on 02 August 2022 at 15:37

score 329 · Answer 6 · 2022-07-17T11:10:57.767000

329

Views

How to check at runtime whether the CPU supports RTM in gcc/clang(++) or inline assembly?

Published on 17 July 2022 at 11:10

score 167 · Answer 7 · 2020-11-25T06:02:35.553000

167

Views

Intel-TSX: why rtm is acting weird?

Published on 25 November 2020 at 06:02

score 267 · Answer 8 · 2020-09-14T21:12:58.560000

267

Views

Intel-TSX: Why rtm is failing?

Published on 14 September 2020 at 21:12

score 911 · Answer 9 · 2020-04-21T04:40:13.293000

911

Views

How to use Intel TSX with C++ memory model?

Published on 21 April 2020 at 04:40

score 1.8k · Answer 10 · 2020-04-20T09:53:22.927000

1.8k

Views

Are Intel TSX prefixes executed (safely) on AMD as NOP?

Published on 20 April 2020 at 09:53

score 877 · Answer 11 · 2020-04-19T19:09:13.523000

877

Views

Has Hardware Lock Elision gone forever due to Spectre Mitigation?

Published on 19 April 2020 at 19:09

score 276 · Answer 12 · 2020-01-16T20:45:24.413000

276

Views

Is it possible to debug Intel TSX?

Published on 16 January 2020 at 20:45

score 320 · Answer 13 · 2019-12-06T08:21:03.297000

320

Views

Assembler xbegin raise Illegal instruction

Published on 06 December 2019 at 08:21

score 180 · Answer 14 · 2019-12-05T19:01:19.227000

180

Views

Using TSX with WebAssembly

Published on 05 December 2019 at 19:01

score 2.3k · Answer 15 · 2019-07-17T16:01:26.757000

2.3k

Views

Enable/Disable Hardware Lock Elision

Published on 17 July 2019 at 16:01

score 818 · Answer 16 · 2018-08-15T11:29:58.180000

818

Views

How to properly use TSX-NI (both HLE and RTM) when threads might switch cores?

Published on 15 August 2018 at 11:29

score 223 · Answer 17 · 2017-12-07T00:57:43.723000

223

Views

Why these rtm transactions act weird?

Published on 07 December 2017 at 00:57

score 192 · Answer 18 · 2017-12-04T02:23:55.160000

192

Views

use 'perf trace command' to a special thread with TSX abort

Published on 04 December 2017 at 02:23

score 156 · Answer 19 · 2017-11-14T11:43:39.547000

156

Views

Program is losing an increment and two ``printf``s

Published on 14 November 2017 at 11:43

score 1.5k · Answer 20 · 2017-11-10T10:08:09.620000

1.5k

Views

How to use "unsafe" in JNI?

Published on 10 November 2017 at 10:08

List Question

Intel TSX: xbegin always returns 0

Intel TSX programming environement

How to know Intel TSX is currently used by other process?

How to enable Intel TSX in i7-7700 cpu?

Understanding ARM Transactional Memory Extensions

How to check at runtime whether the CPU supports RTM in gcc/clang(++) or inline assembly?

Intel-TSX: why rtm is acting weird?

Intel-TSX: Why rtm is failing?

How to use Intel TSX with C++ memory model?

Are Intel TSX prefixes executed (safely) on AMD as NOP?

Has Hardware Lock Elision gone forever due to Spectre Mitigation?

Is it possible to debug Intel TSX?

Assembler xbegin raise Illegal instruction

Using TSX with WebAssembly

Enable/Disable Hardware Lock Elision

How to properly use TSX-NI (both HLE and RTM) when threads might switch cores?

Why these rtm transactions act weird?

use 'perf trace command' to a special thread with TSX abort

Program is losing an increment and two ``printf``s

How to use "unsafe" in JNI?

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