I am writing some programs which contains RTM transactional regions. I have checked my machine supports HLE and RTM using cpuid instruction. However, I notice that the xbegin instruction always returns zero (the value in rax register), which indicates that the transaction is aborted. So I write a quite simple demo using xbegin and xend instruction, and do not insert any instructions between them.
The code described above is:
int main() {
asm volatile(".byte 0xc7, 0xf8, 0x03, 0x00, 0x00, 0x00" ::"r"(-1ul)); // xbegin machine code
asm volatile(".byte 0x0f, 0x01, 0xd5"); // xend machine code
return 0;
}
The corresponding assembly code is:
00000000000005fa <main>:
5fa: 48 c7 c0 ff ff ff ff mov $0xffffffffffffffff,%rax
601: c7 f8 03 00 00 00 xbeginq 60a <main+0x10>
607: 0f 01 d5 xend
60a: b8 00 00 00 00 mov $0x0,%eax
60f: c3 retq
In this code, I set the fallback address in xbegin with the address of the next instruction of xend. So whether the transaction aborts or not, the code can finish execution normally. Then I use perf to profile the execution of this code, and I find that this transaction aborts due to HLE-unfriendly instructions. I don't know the reason.
$ sudo perf stat -e rtm_retired.start ./demo
Performance counter stats for './demo':
1 rtm_retired.start
0.000614539 seconds time elapsed
0.000634000 seconds user
0.000000000 seconds sys
$ sudo perf stat -e rtm_retired.commit ./demo
Performance counter stats for './demo':
0 rtm_retired.commit
0.000657118 seconds time elapsed
0.000616000 seconds user
0.000000000 seconds sys
$ sudo perf stat -e rtm_retired.aborted_unfriendly ./demo
Performance counter stats for './demo':
1 rtm_retired.aborted_unfriendly
0.000617362 seconds time elapsed
0.000609000 seconds user
0.000000000 seconds sys
My machine configuration:
CPU: Intel(R) Core(TM) i7-6700 CPU @ 3.40GHz
microcode: 0xf0
OS: Linux 5.4.0-150-generic, Ubuntu 18.04.1
Update: I have noticed an article, which means that Intel has disabled TSX through a microcode update. They added an new CPUID bit to indicate this change. I have checked this bit and found that it is set on my processor. So the RTM regions cannot be executed successfully.
I have noticed an article, which means that Intel has disabled TSX through a microcode update. They added an new CPUID bit to indicate this change. I have checked this bit and found that it is set on my processor. So the RTM regions cannot be executed successfully.