inout port with real datatype in systemverilog

Question

I need to have an inout port with real dataytype in my module. Also I need to have multiple driver resolution capability in that port. (Saw about nettype, but didn't see usage of that in module ports in LRM)

Here is a sample code.

module abc (
  input real vref1, 
  output real vout);

  assign vout = vref1 * 3.17;
endmodule

module def (
  input logic out_en, 
  input logic data, 
  output logic vref1);

  bufif1 b1 (vref1, data, out_en);
endmodule

module top (
  inout real vref1,
  input logic out_en,
  input logic data,
  output real vout);
  
  logic vref1_dig_l;

  assign vref1 = (vref1_dig_l === 1'bz) ? 100.0 : ((vref1_dig_l == 1'b0) ? 0.0 : 20.0);

  abc a1 (vref1, vout);
  def d1 (out_en, data, vref1_dig_l);
endmodule

module temp ();
  real  vref1;
  logic out_en;
  logic data;
  real vout;

  top t1 (vref1, out_en, data, vout);

  initial 
    $monitor("vref1 - %0f, out_en - %0b, data - %0b, vout - %0f", vref1, out_en, data, vout);

  initial begin
    #1 vref1 = 5.0; out_en = $random()%2; data = $random();
    #1 vref1 = 5.0; out_en = $random()%2; data = $random();
    #1 vref1 = 5.0; out_en = $random()%2; data = $random();
    #1 vref1 = 5.0; out_en = $random()%2; data = $random();
    #1 vref1 = 5.0; out_en = $random()%2; data = $random();
    #1 vref1 = 5.0; out_en = $random()%2; data = $random();
    #1 vref1 = 5.0; out_en = $random()%2; data = $random();
    #1 vref1 = 5.0; out_en = $random()%2; data = $random();
  end
endmodule

This is giving me the following error -

  inout real vref1,
                 |
xmvlog: *E,SVNTRL (../b.sv,25|17): A module port that is a net cannot be of type 'real' or 'shortreal' by SystemVerilog language rules.

Answer 1

you can use the following:

nettype real nreal;

module top (
  inout nreal vref1,
  ...

however, real is not a synthesizable concept and cannot be used in the gate-level logic, so the following is illegal: bufif1 b1 (vref1, data, out_en) with verif1 as real.

Another way to work around your issues is using of system verilog functions for conversion real to bits and vice versa (lrm 20.5)

    [63:0] $realtobits ( real_val )
    real $bitstoreal ( bit_val )

for assignment issues in the init block of the temp module:

by verilog rules lhs of any assignment from a procedural block must be a variable. 'initial' block is a procedural block. 'net' is not a variable.

In temp you have to declare vref1 as 'nreal', which is a net type and you cannot assign it from a procedural block. You would need a varialbe as an intermediate stage:

nreal vref1;
real vref1_real;
assign nreal = vref1_real;

...
initial begin
    vref1_real = your expression;
...

The above would fix your assignment issues.

It also looks like in your case a resolution function is needed. Something like the following can help:

function automatic real nres_avg (input real drivers[]);
    return drivers.sum/drivers.size(); // average of all drivers
endfunction
nettype real nreal with nres_avg;

Answer 2

The built-in net object like wire, tri, wand, etc. cannot have a data type other than those made up from the 4-state type logic. The built-in nets all have pre-defined resolution functions for when there are multiple drivers.

An inout is expected to have multiple drivers, so only nets are allowed on that kind of port. If you want a real datatype on a net, it needs to be defined with user defined nettype so a resolution function can be associated with the net. i.e. do you want the individual drivers to be averaged, summed, max value, etc. There are some examples in the 1800-2017, and most tools provide these as readily available packages.