what is the actual and exact meaning of memory mapped terms used in context of register-interfaces in fpga design?

Question

So many times, I have heard these terms in the FPGA design process, and to my knowledge, which I gather from a Google search, it's like some data is going to be transmitted from the core to memory.

Let's say a system where the 1st block is Zynq ps (cortex A-9 processor core) and the 2nd block is AXI GPIO, which is connected through some intermediate interfaces (AXI interconnect), so processors treat axi gpio as memory. This is what I know through some sources, but I want to actually feel it and digest it so, I need proper explanation.

When we get to know that it is memory-mapped in the context of registers, and interfaces. In general, a register is always memory, so we say it's memory-mapped Register and in the context of processor a how do we know that it is a memory-mapped interface?

Answer 1

A memory mapped interface is one that can be accessed by the CPU as if it was memory. In particular the same instructions (and often also address space) can be used to access the peripheral.

Memory would behave such that a value written to a certain address could be read back again from there unchanged. However, a memory mapped peripheral is not necessarily behaving as memory. Instead it can have behaviors such as

• write only addresses, for instance to issue a command when a certain bit is set. The value read back might always be 0.
• read only addresses, to feed data to the CPU. For instance status registers. They could have a different value every time they are read
• side effects on read or write. For instance a message could be transmitted everytime a register is written
• of course it can also contain just plain memory behind certain registers. For instance for a message buffer.

A main advantage is that the CPU and Software do not need special instructions to access it, they might not even meet to "know".

A drawback can be that the CPU or Software not knowing about it, might introcude errors. For instance a compiler could optimize out a write access to a memory mapped register, assuming it was never read. Or speculative caching might trigger side effects in the peripheral if the MMU is not correctly configured.