VHDL signal timing check with signal duration info

Question

I would like to test the VHDL signal for the condition:

• Signal S stays for minimum X ns without changing the value
• If the checking condition fails, it can tell me how long does signal S stay stably

Here is the example that I have done:

process begin
wait on S'event;
assert S'delayed'stable(X ns) report time'image(now) & " " & time'image(S'last_event) & " " & time'image(S'last_active) severity failure;
end process;

The print value of S'last_event and S'last_active are always zero, is there any way to know if the assertion failure occurs, how long does the signal S stays stable?

I have checked out this website example: http://www.markharvey.info/rtl/attr_15.11.2015/attr_15.11.2015.html

And understood why S'last_event and S'last_active are always zero (checkout this: http://computer-programming-forum.com/42-vhdl/45e8be4a6813284e.htm)

I need the solution to tell me how long does signal S stay stably before the S'event occurs.

Any solution without implementing a counter? Or any library from OSVVM and Vunit?

Answer 1

What about the following?

process
  variable t: time := 0 ns;
begin
  wait on s;
  assert now - t > X ns report time'image(now - t) severity failure;
  t := now;
end process;