Python: Code for VHDL Code Generator

Question

I am trying to make a ROM in VHDL language, I am using this template I found on http://www.edaboard.com/thread38052.html :

library ieee;
use ieee.std_logic_1164.all;

entity ROM is
port ( address : in std_logic_vector(3 downto 0);
     data : out std_logic_vector(7 downto 0) );
end entity ROM;

architecture behavioral of ROM is
type mem is array ( 0 to 2**4 - 1) of std_logic_vector(7 downto 0);
constant my_Rom : mem := (
0  => "00000000",
1  => "00000001",
2  => "00000010",
3  => "00000011",
4  => "00000100",
5  => "11110000",
6  => "11110000",
7  => "11110000",
8  => "11110000",
9  => "11110000",
10 => "11110000",
11 => "11110000",
12 => "11110000",
13 => "11110000",
14 => "11110000",
15 => "11110000");
begin
process (address)
begin
 case address is
   when "0000" => data <= my_rom(0);
   when "0001" => data <= my_rom(1);
   when "0010" => data <= my_rom(2);
   when "0011" => data <= my_rom(3);
   when "0100" => data <= my_rom(4);
   when "0101" => data <= my_rom(5);
   when "0110" => data <= my_rom(6);
   when "0111" => data <= my_rom(7);
   when "1000" => data <= my_rom(8);
   when "1001" => data <= my_rom(9);
   when "1010" => data <= my_rom(10);
   when "1011" => data <= my_rom(11);
   when "1100" => data <= my_rom(12);
   when "1101" => data <= my_rom(13);
   when "1110" => data <= my_rom(14);
   when "1111" => data <= my_rom(15);
   when others => data <= "00000000";
 end case;
  end process;
  end architecture behavioral;

Well, the problem is that I want to put in my ROM 2000 values. So I was wondering how to make the next using python:

Imagine you have in a .txt file this data in the next format:

0  45
1  56
2  78
3  98

So the program would do this with the data:

0 => "00101101"
1 => "00111000"
2 => "01001110"
3 => "01100010"

Well these values "00101101","00111000","01001110","01100010" are the respectives values for the binary representation of 45,56,78 y 89. So, you get the idea...

There is a small detail, it is needed to specify the number of bits for the representation: If you don´t you could get this:

0 => "101101"
1 => "111000"
2 => "1001110"
3 => "1100010"

Thank you so much to all possible pieces of code to do this program

Answer 1

for line in open('your_file.txt'):
    s = line.strip().split("  ") # two spaces are for split
    p = '{} => "{:0{min_bits}b}"'.format(s[0], int(s[1]), min_bits=10)
    print p

Answer 2

Try this:

bit_count = 8
format_template = '{{0}} => "{{1:0{0}b}}"'.format(bit_count)
with open(r"input_file.txt") as input_file:
    for line in input_file:
        data = map(int, line.split())
        print format_template.format(*data)

Answer 3

As an alternative to the other answers, make your ROM store naturals or integers (as appropriate). Then your constant can be of the form:

0 => 45,
1 => 56, ...

etc.

If you have all the values already, you could just put them all in a big comma separator series without doing the n => positional mapping.

(45, 56, 78, 98,....)

Also, if you make your address input a numerical type (either unsigned or natural as you prefer) you can simplify your address decode as just

data <= my_rom(address);

or

data <= my_rom(to_integer(address));

Answer 4

Here is another method; using the toVHDL converter in MyHDL. You can use arbitrary Python expressions to initialize a tuple.

This is the MyHDL description:

from myhdl import *

def VhdlRomGen(addr, data):

    # Create the ROM container
    rom = [Signal(intbv(0)[8:]) for ii in range(2**4)]

    # Initialize ROM, any value, any complex python can
    # be in this initialization code.
    for ii in xrange(len(rom)):
        rom[ii] = ii

    rom = tuple(rom)

    @always_comb
    def rtl_rom():
        data.next = rom[int(addr)]


    return rtl_rom

if __name__ == "__main__":
    addr = Signal(intbv(0)[4:])
    data = Signal(intbv(0)[8:])

    toVHDL(VhdlRomGen, addr, data)

And this is the converted VHDL:

-- Generated by MyHDL 0.7
-- Date: Sat May 21 15:39:27 2011


library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;

use work.pck_myhdl_07.all;

entity VhdlRomGen is
        port (
            addr: in unsigned(3 downto 0);
            data: out unsigned(7 downto 0)
        );
end entity VhdlRomGen;


architecture MyHDL of VhdlRomGen is
begin

VHDLROMGEN_RTL_ROM: process (addr) is
begin
    case to_integer(addr) is
        when 0 => data <= "00000000";
        when 1 => data <= "00000001";
        when 2 => data <= "00000010";
        when 3 => data <= "00000011";
        when 4 => data <= "00000100";
        when 5 => data <= "00000101";
        when 6 => data <= "00000110";
        when 7 => data <= "00000111";
        when 8 => data <= "00001000";
        when 9 => data <= "00001001";
        when 10 => data <= "00001010";
        when 11 => data <= "00001011";
        when 12 => data <= "00001100";
        when 13 => data <= "00001101";
        when 14 => data <= "00001110";
        when others => data <= "00001111";
    end case;
end process VHDLROMGEN_RTL_ROM;
end architecture MyHDL;