Why Vacant locations in the address space are never accessible in RISC-V ISA?

Question

I am reading The RISC-V Instruction Set Manual Volume I: Unprivileged ISA and i encountered a very strange statement to me. In subsection 1.4 Memory at the end of fifth paragraph is stated "Vacant locations in the address space are never accessible." I am a bit confused and searched about that but i couldn't come up with any conclusion. It would be appreciated if you share your idea with me.

Answer 1

Why Vacant locations in the address space are never accessible in RISC-V ISA?

This is by definition.  From the second paragraph in section 1.4:

Different address ranges of a hart’s address space may (1) be vacant, or (2) contain main memory, or (3) contain one or more I/O devices.

So, this is saying that there may be address ranges that have neither memory nor I/O devices: and these are called vacant locations.

Ordinarily, if an instruction attempts to access memory at an inaccessible address, an exception is raised for the instruction.  Vacant locations in the address space are never accessible.

And further that such vacant locations are inaccessible meaning that attempting to access them will fault (cause an exception).

The hart is (programmable by the operating system to be) aware of three kinds of address ranges: main memory, I/O devices, and vacant (i.e. neither).  Attempts to execute a load or a store at a vacant location will fault because there's nothing there to access, and the hart knows this (i.e. it has been told what ranges are valid/invalid).