AXI bus to Wishbone Wrapper

Question

Could anyone please tell me about the AXI bus and its signals. I would also want to know about AXI bus to wishbone bus wrapper to implement it in VHDL. I am looking at the implementation of a register in FPGA and then give the corresponding commands from LINUX to drive the LED's on a zedboard. wishbone bus is used to transfer the data and make communication with the register.

Answer 1

Here are some documents for the AMBA (Advanced Microcontroller Bus Architecture) including AXI and AXI-Light:

• Xilinx UG761 - AXI Reference Guide
• ARM - AMBA Open Specifications
• Wikipedia article

If you are going to write a GPIO to register mapping module for WishBone, why don't you write a AXI to register / GPIO mapper and spare the AXI2WB bridge?

I thought OpenCores has a AXI2WB wrapper, but I can't find it.

Answer 2

I know, that this is an old question, but as there is no answer providing link to the right HDL source, I'd like to propose a few:

1. There is an AXI to WB bridge written in Verilog by Daniel Strother (it was written in 2011)
2. On OpenCores there is a very simple AXI4-Lite to Wishbone bridge (the project contains also AXI4-Lite to IPbus bridge) written in VHDL by me and my colleague.