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Cause of unconnected node warnings in verilog code

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I am writing code that performs the trapezoidal integration method. The code has the FPGA clock (I'm using the Mimas Spartan 6), SIGNAL (the new point to be accounted for in the integration), x (the interval between points), and SUM (the result of the past integrations for inputs, and the output is OUT. Since there must be two inputs to the trapezoidal method, there are two registers yregone and yregtwo, so that SIGNAL is set to yregone and yregtwo is set to the old yregone (the past SIGNAL). The two are added, then bit shifted over so that it's divided by two, multiplied by x, and then have SUM added (OUT is mapped to SUM on the board).

The code compiles with the warnings given. I had read elsewhere that warnings could be ignored. The code compiled despite the errors so I attempted to download the code onto the board and it said that configuration failed. Therefore I assumed that the warnings must point out some error in the code that must be fixed. What is wrong?

Code

module trapverilog(
    input CLK,
     input signed [7:0] SIGNAL,
     input [7:0] x,
     input signed [20:0] SUM, // OUT pins are mapped to SUM pins on board
     output reg OUT1,
     output reg OUT2,
     output reg OUT3,
     output reg OUT4,
     output reg OUT5,
     output reg OUT6,
     output reg OUT7,
     output reg OUT8,
     output reg OUT9,
     output reg OUT10,
     output reg OUT11,
     output reg OUT12,
     output reg OUT13,
     output reg OUT14,
     output reg OUT15,
     output reg OUT16,
     output reg OUT17,
     output reg OUT18,
     output reg OUT19,
     output reg OUT20
    );

reg signed [7:0] yregone;
reg signed [7:0] yregtwo;
reg signed [20:0] innerSumOutput;
reg signed [20:0] innerSum;

function [20:0] multiply;
    input signed [7:0] a;
    input signed [7:0] b;
    reg [15:0] a1, a2, a3, a4, a5, a6, a7, a8;
    begin
        a1 = (b[0]==1'b1) ? {8'b00000000, a} : 16'b0000000000000000;
        a2 = (b[1]==1'b1) ? {7'b0000000, a, 1'b0} : 16'b0000000000000000;
        a3 = (b[2]==1'b1) ? {6'b000000, a, 2'b00} : 16'b0000000000000000;
        a4 = (b[3]==1'b1) ? {5'b00000, a, 3'b000} : 16'b0000000000000000;
        a5 = (b[4]==1'b1) ? {4'b0000, a, 4'b0000} : 16'b0000000000000000;
        a6 = (b[5]==1'b1) ? {3'b000, a, 5'b00000} : 16'b0000000000000000;
        a7 = (b[6]==1'b1) ? {2'b00, a, 6'b000000} : 16'b0000000000000000;
        a8 = (b[7]==1'b1) ? {1'b0, a, 7'b0000000} : 16'b0000000000000000;
        multiply = a1 + a2 + a3 + a4 + a5 + a6 + a7 + a8;
    end
endfunction

always @(posedge CLK)
begin
    yregtwo <= yregone;
    yregone <= SIGNAL;

    if (yregone != 0)
    begin
        innerSum <= multiply((yregone + yregtwo), x); // treats x as plain h, change if treated as h/2 // multiply defined by function shift-adds
        innerSumOutput <= (innerSum <<< 1) + SUM; // <<< is signed one bit shift which = /2
        OUT20 <= innerSumOutput[20];
        OUT1 <= innerSumOutput[1]; // OUT is two's complement
        OUT2 <= innerSumOutput[2];
        OUT3 <= innerSumOutput[3];
        OUT4 <= innerSumOutput[4];
        OUT5 <= innerSumOutput[5];
        OUT6 <= innerSumOutput[6];
        OUT7 <= innerSumOutput[7];
        OUT8 <= innerSumOutput[8];
        OUT9 <= innerSumOutput[9];
        OUT10 <= innerSumOutput[10];
        OUT11 <= innerSumOutput[11];
        OUT12 <= innerSumOutput[12];
        OUT13 <= innerSumOutput[13];
        OUT14 <= innerSumOutput[14];
        OUT15 <= innerSumOutput[15];
        OUT16 <= innerSumOutput[16];
        OUT17 <= innerSumOutput[17];
        OUT18 <= innerSumOutput[18];
        OUT19 <= innerSumOutput[19];
    end
end

endmodule

UCF

NET "CLK" LOC = P126;
NET "SIGNAL[0]" LOC = P35 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
NET "SIGNAL[1]" LOC = P34 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
NET "SIGNAL[2]" LOC = P33 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
NET "SIGNAL[3]" LOC = P32 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
NET "SIGNAL[4]" LOC = P30 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
NET "SIGNAL[5]" LOC = P29 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
NET "SIGNAL[6]" LOC = P27 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
NET "SIGNAL[7]" LOC = P26 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
NET "x[0]" LOC = P24 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
NET "x[1]" LOC = P23 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
NET "x[2]" LOC = P22 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
NET "x[3]" LOC = P21 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
NET "x[4]" LOC = P17 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
NET "x[5]" LOC = P16 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
NET "x[6]" LOC = P15 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
NET "x[7]" LOC = P14 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
NET "SUM[0]" LOC = P12 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
NET "SUM[1]" LOC = P11 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
NET "SUM[2]" LOC = P10 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET "SUM[3]" LOC = P9 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET "SUM[4]" LOC = P8 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET "SUM[5]" LOC = P7 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET "SUM[6]" LOC = P6 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET "SUM[7]" LOC = P5 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET "SUM[8]" LOC = P2 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET "SUM[9]" LOC = P1 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET "SUM[10]" LOC = P142 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET "SUM[11]" LOC = P141 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET "SUM[12]" LOC = P140 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET "SUM[13]" LOC = P139 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET "SUM[14]" LOC = P138 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET "SUM[15]" LOC = P137 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET "SUM[16]" LOC = P134 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET "SUM[17]" LOC = P133 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET "SUM[18]" LOC = P132 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET "SUM[19]" LOC = P131 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET "SUM[20]" LOC = P43 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET "OUT1" LOC = P44 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET "OUT2" LOC = P45 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET "OUT3" LOC = P46 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET "OUT4" LOC = P47 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET "OUT5" LOC = P48 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ; 
NET "OUT6" LOC = P50 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET "OUT7" LOC = P51 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET "OUT8" LOC = P55 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET "OUT9" LOC = P56 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ; 
NET "OUT10" LOC = P74 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET "OUT11" LOC = P75 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET "OUT12" LOC = P78 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET "OUT13" LOC = P79 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET "OUT14" LOC = P80 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET "OUT15" LOC = P81 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET "OUT16" LOC = P82 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET "OUT17" LOC = P83 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET "OUT18" LOC = P84 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET "OUT19" LOC = P85 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET "OUT20" LOC = P87 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;

Warnings

WARNING:Xst:2677 - Node <innerSum_20> of sequential type is unconnected in block <trapverilog>.
WARNING:Xst:2677 - Node <innerSumOutput_0> of sequential type is unconnected in block <trapverilog>.
WARNING:Xst:2677 - Node <innerSum_20> of sequential type is unconnected in block <trapverilog>.
WARNING:Xst:2677 - Node <innerSumOutput_0> of sequential type is unconnected in block <trapverilog>.
WARNING:Xst:1710 - FF/Latch <innerSum_19> (without init value) has a constant value of 0 in block <trapverilog>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <innerSum_16> (without init value) has a constant value of 0 in block <trapverilog>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <innerSum_17> (without init value) has a constant value of 0 in block <trapverilog>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <innerSum_18> (without init value) has a constant value of 0 in block <trapverilog>. This FF/Latch will be trimmed during the optimization process.
WARNING:Security:42 - Your software subscription period has lapsed. Your current
WARNING:Security:42 - Your software subscription period has lapsed. Your current version of Xilinx tools will continue
WARNING:Par:288 - The signal SUM<0>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:283 - There are 1 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
configuration verilog fpga compiler-warnings spartan
Original Q&A
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There are 1 best solutions below

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Barry Moss On

You need to understand the warnings that the tools give you, not just ignore them. It looks like you have a lot of unconnected signals and FF/Latches with constant values in your design--that probably means it won't do what you want it to do even if you do manage to download it. The last PAR warning indicates a DRC error, which may be the source of your problems because Bitgen isn't sure what to do with your loadless signal. Try cleaning up the warnings (or at least make sure you understand all of them and know which ones are safe to disregard) and then try again.

Does your design simulate OK? If the answer is "What simulation?" I'd seriously suggest you make sure you can run a simple simulation of your design before you synthesize and PAR it.

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