Does SystemVerilog Generate support delays?

Question

I thought of generating clock using genvar like below:

        reg [7:0]clk;  
      
     genvar i;
        generate
          for (i=0; i < 7; i++) begin
              #1 clk[i]=~clk[i];
            end
        endgenerate

I am getting an error:

error: near "#": syntax error, unexpected '#'

How can we resolve it? Can I use delays inside generate block?

Answer 1

Yes, generate blocks support delays. To fix your problem, use a procedural always block:

reg [7:0] clk;  

genvar i;
generate
    for (i=0; i < 7; i++) begin
        always #1 clk[i]=~clk[i];
    end
endgenerate

Answer 2

I feel it isn't necessary to have a generate, you can use the for loop directly in an always block:

reg [7:0] clk;
integer i;
always begin
  #1;
  for(i = 0; i < 7; i = i + 1)
    clk[i] = ~clk[i];
end

Nevertheless, if all the bits are toggled at the same time, you can simplify it with:

always
  #1 clk = ~clk; //..bitwise invert the array

Answer 3

It looks like OP wanted to have a sequential delay model. In this case the code should look like this:

always begin
  for(i = 0; i < 7; i = i + 1)
    #1 clk[i] = ~clk[i];
end