Fail to connect self-defined periphery to the pbus in rocket-chip project

Question

Following the demo in chipyard doc I create a self-defined Mac, a client node connected to fbus and a master node connected to pbus.

  class Mac(implicit p: Parameters) extends LazyModule with HasMacParameters{


  val tlMasterNode =   
        TLManagerNode(Seq(TLSlavePortParameters.v1(
          managers = Seq(TLSlaveParameters.v1(
          address = Seq(AddressSet(0x30000000L, 0x0FFFL)),
          regionType = RegionType.VOLATILE,
          executable = false,
          supportsGet         = TransferSizes(32/8, 32/8),
          supportsPutFull     = TransferSizes(32/8, 32/8),
          supportsPutPartial  = TransferSizes(32/8, 32/8)
        )),
        beatBytes = 32/8)))


  val tlClientNode = TLClientNode(Seq(TLMasterPortParameters.v1(
    Seq(TLMasterParameters.v1(
      name = "tlMst",
      sourceId = IdRange(0, 1),
    ))
  )))



  // DTS
  val dtsdevice = new SimpleDevice("mac",Seq("mac_0"))

  val int_node = IntSourceNode(IntSourcePortSimple(num = 1, resources = dtsdevice.int))


  lazy val module = new MacImp(this)


}

and trait like this:

trait WithManyMacMix { this: BaseSubsystem =>

    val mac0 = LazyModule(new Mac)

    fbus.coupleFrom("mac_mst") { _ := TLBuffer() := mac0.tlClientNode }
    pbus.coupleTo("mac_cfg")   { mac0.tlMasterNode := TLFragmenter(1,4) :=_ }  //

    ibus.fromSync := mac0.int_node

}

However, it throws exception that failed at pbus.

java.lang.IllegalArgumentException: requirement failed: mac0 has TransferSizes[1, 4], needed PutFull(TransferSizes[4, 4]) or Get(TransferSizes[4, 4])

How can I fix it?