I have 2 questions about CSR file. (I am targeting sodor, a 5-stage pipelined cpu as a core)
[Timing behavior] Is CSR a combinational logic? I mean, does CSR response on the cycle where request was sent? If not, what is the scenario that CSR File takes multiple cycles to process request?
When should I access CSR? Is there any case that I need to approach CSR even if CPU is not processing CSR instruction?
+) If there is any document that explains how the CSR works, please let me know.
What I'm currently guessing is, CSR responses on the cycle where request was sent.
For CSR file access condition, I'm guessing CSR is accessed when 1) When there is CSR instruction(CSRRW, CSRRC, ...) or cpu got external interrupt.